At TSMC’s North American Expertise Symposium on Wednesday, the corporate detailed each its semiconductor expertise and chip-packaging expertise highway maps. Whereas the previous is vital to protecting the standard a part of Moore’s Legislation going, the latter might speed up a development towards processors comprised of increasingly silicon, main shortly to techniques the scale of a full silicon wafer. Such a system, Tesla’s subsequent technology Dojo coaching tile is already in manufacturing, TSMC says. And in 2027 the foundry plans to supply expertise for extra complicated wafer-scale techniques than Tesla’s that might ship 40 occasions as a lot computing energy as at this time’s techniques.
For many years chipmakers elevated the density of logic on processors largely by cutting down the realm that transistors take up and the scale of interconnects. However that scheme has been working out of steam for some time now. As an alternative, the business is popping to superior packaging expertise that enables a single processor to be comprised of a bigger quantity of silicon. The dimensions of a single chip is hemmed in by the biggest sample that lithography gear could make. Referred to as the reticle restrict, that’s at the moment about 800 sq. millimeters. So if you’d like extra silicon in your GPU you have to make it from two or extra dies. The secret’s connecting these dies in order that indicators can go from one to the opposite as shortly and with as little power as in the event that they had been all one massive piece of silicon.
TSMC already makes a wafer-size AI accelerator for Cerebras, however that association seems to be distinctive and is totally different from what TSMC is now providing with what it calls System-on-Wafer.
In 2027, you’ll get a full-wafer integration that delivers 40 occasions as a lot compute energy, greater than 40 reticles’ value of silicon, and room for greater than 60 high-bandwidth reminiscence chips, TSMC predicts
For Cerebras, TSMC makes a wafer filled with an identical arrays of AI cores which might be smaller than the reticle restrict. It connects these arrays throughout the “scribe strains,” the areas between dies which might be often left clean, so the wafer might be diced up into chips. No chipmaking course of is ideal, so there are all the time flawed elements on each wafer. However Cerebras designed in sufficient redundancy that it doesn’t matter to the completed laptop.
Nevertheless, with its first spherical of System-on-Wafer, TSMC is providing a special resolution to the issues of each reticle restrict and yield. It begins with already examined logic dies to attenuate defects. (Tesla’s Dojo comprises a 5-by-5 grid of pretested processors.) These are positioned on a provider wafer, and the clean spots between the dies are crammed in. Then a layer of high-density interconnects is constructed to attach the logic utilizing TSMC’s built-in fan-out expertise. The purpose is to make knowledge bandwidth among the many dies so excessive that they successfully act like a single massive chip.
By 2027, TSMC plans to supply wafer-scale integration primarily based on its extra superior packaging expertise, chip-on-wafer-on-substrate (CoWoS). In that expertise, pretested logic and, importantly, high-bandwidth reminiscence, is hooked up to a silicon substrate that’s been patterned with high-density interconnects and shot by means of with vertical connections referred to as through-silicon vias. The hooked up logic chips can even benefit from the corporate’s 3D-chip expertise referred to as system-on-integrated chips (SoIC).
The wafer-scale model of CoWoS is the logical endpoint of an growth of the packaging expertise that’s already seen in top-end GPUs. Nvidia’s subsequent GPU, Blackwell, makes use of CoWos to combine greater than 3 reticle sizes’ value of silicon, together with 8 high-bandwidth reminiscence (HBM) chips. By 2026, the corporate plans to increase that to five.5 reticles, together with 12 HBMs. TSMC says that may translate to greater than 3.5 occasions as a lot compute energy as its 2023 tech permits. However in 2027, you may get a full wafer integration that delivers 40 occasions as a lot compute, greater than 40 reticles’ value of silicon and room for greater than 60 HBMs, TSMC predicts.
What Wafer Scale Is Good For
The 2027 model of system-on-wafer considerably resembles expertise referred to as Silicon-Interconnect Cloth, or Si-IF, developed at UCLA greater than 5 years in the past. The group behind SiIF contains electrical and computer-engineering professor Puneet Gupta and IEEE Fellow Subramanian Iyer, who’s now charged with implementing the packaging portion of the USA’ CHIPS Act.
Since then, they’ve been working to make the interconnects on the wafer extra dense and so as to add different options to the expertise. “If you would like this as a full expertise infrastructure, it must do many different issues past simply offering fine-pitch connectivity,” says Gupta, additionally an IEEE Fellow. “One of many greatest ache factors for these massive techniques goes to be delivering energy.” So the UCLA group is engaged on methods so as to add good-quality capacitors and inductors to the silicon substrate and integrating gallium nitride energy transistors.
AI coaching is the apparent first utility for wafer-scale expertise, however it’s not the one one, and it could not even be the very best, says College of Illinois Urbana-Champaign laptop architect and IEEE Fellow Rakesh Kumar. On the Worldwide Symposium on Pc Structure in June, his group is presenting a design for a wafer-scale community swap for knowledge facilities. Such a system might lower the variety of superior community switches in a really massive—16,000-rack—knowledge heart from 4,608 to simply 48, the researchers report. A a lot smaller, enterprise-scale, knowledge heart for say 8,000 servers might get through the use of a single wafer-scale swap.
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